The present invention relates to an SRAM.
Along with the recent increase in capacity and reduction in chip size of SRAMs (Static Random Access Memories), there is a demand for further miniaturization of memory cells. FIG. 7 shows FIG. 1 of Japanese Unexamined Patent Application Publication No. 10-135355. The SRAM shown in FIG. 7 is a complete CMOS (Complementary Metal Oxide Semiconductor) type SRAM, and includes four NMOS transistors and two PMOS transistors. Specifically, the SRAM includes two access transistors AT11 and AT12 which are NMOS transistors; two drive transistors DT11 and DT12 which are NMOS transistors; and two drive transistors LT11 and LT12 which are PMOS transistors. Each area indicated by the dashed line in FIG. 7 represents a contact CT. Each hatched area represents a diffusion region DA.
As shown in FIG. 7, a gate electrode G11a of the NMOS transistor DT11 for driving and a gate electrode G11b of the PMOS transistor LT11 for loading, which have been integrally formed up to now, are separated from each other. Similarly, a gate electrode G12a of the NMOS transistor DT12 for driving and a gate electrode G12b of the PMOS transistor LT12 for loading, which have been integrally formed up to now, are separated from each other. This configuration prevents mutual diffusion of p-type impurities and n-type impurities in the gate electrodes.